This invention relates to semiconductor memory devices, and more specifically to a nonvolatile memory cell having a single vertical JFET device with a capacitively coupled source having variable capacitance characteristics. Non-volatile memories have distinct advantages over dynamic and static memories, in that data is not lost when operating power is removed and rapid refresh cycles are not required.
In U.S. patent application Ser. No. 228,413 filed Jan. 26, 1981, Bate discloses a non-volatile cell called a non-volatile JRAM which contains a single vertical channel JFET device as an addressed gate underneath an MIS gate which utilizes a nonvolatile insulator. Using appropriate voltage waveforms on the MIS gate and JFET gate, nonvolatile states can be written to place positive or negative charge into the memory insulator by placing large negative or positive voltages on the MIS gate when the JFET channel is open.
The nonvolatile state of the memory insulator is read by (1) attempting to reverse bias the JFET source immediately beneath the MIS gate by applying an appropriate voltage to the MIS gate before and during closing of the JFET channel and then, (2) determining whether a reverse bias was obtained by floating the MIS gate and observing its voltage change when the JFET channel is reopened. In patent application (Ser. No. 269,201, filed June 2, 1981), the same read mechanism is used, but the nonvolatile states are written using only one sign of voltage on either the MIS gate or the JFET gate. The present invention improves the read mechanism used in patent application Ser. Nos. 228,413 and 269,201 in two major ways. These two applications read the nonvolatile state of the memory insulator by attempting to reverse bias the JFET source. The reverse biased JFET source can be discharged by the flow of current to the source from the JFET gate, the semiconductor substrate, the semiconductor surface, or the depletion layers separating these regions. These currents can be larger in high capacitance cells such as cells with MNOS capacitors due to edge effects associated with large electric fields and fabrication process induced defects.
If the reverse bias is discharged before the volatile state can be sensed, then the nonvolatile state of the insulator cannot be read. The present invention overcomes this difficulty by sensing the voltage feedthrough from word line to bit line which will depend on the absence or presence of an inversion layer underneath the memory insulator depending on the programmed state of the memory insulator. Since the inversion layer will be present or absent at equilibrium, there is no need to preset a nonequilibrium reverse bias and there is no sensitivity to dark currents. The other major improvement is that since a reverse bias does not have to be preset, no voltage pulse has to be applied to the bit line which would normally have a small disturbing effect on the nonvolatile state of the memory insulator.
The present invention is also an improvement over MNOS DRAM cells as related in an article by R. Kondo, "Dynamic Injection NMOS Memory Devices", Japanese Journal of Applied Physics, Vol. 19, Supplement 19-1, p. 231-237, 1980, where the larger dark currents associated with NMOS edge effects and the nonequilibrium voltage states caused the same deleterious effects described above for the NVJRAM cells with the read mechanism of patent application Ser. No. 228,413.
Crosspoint nonvolatile capacitor cells placed at the intersection of orthogonal bit or word lines but without nonvolatile JRAM's have been investigated by J. I. Raffel and J. A. Yasaitis, "Programmable Read-Only Memories", 1977 International Solid States Circuits Conference, p. 190-193 and 251, 1977, using a voltage ramp on the word line and sensing the capacitive feedthrough to the bit line. The present invention utilizes a more sensitive detection scheme in which a voltage step or pulse rather than a ramp is applied to the word line in a state-of-the-art DRAM sense latch is used to sense the small voltage feedthrough and then latch to a voltage such as zero volts in one state and +5 volts in the other state, depending on the written state of the memory insulator. In the present invention, the effect of nonselected cells on sensitivity is removed by reverse biasing all nonselected cell word lines sufficiently to pull out an inversion layer which may have been previously programmed in some cells.
In the past, MNOS capacitors have been used with a static RAM cell as related by S. Saito et al, "N-Channel High Speed Nonvolatile Static RAM Utilizing MNOS Capacitors", Japan Journal of Applied Physics, Vol. 19, Supplement 19-1, pages 225-229, 1980, to provide nonvolatile information storage backup in the case of loss of electrical power. In this previous cell, one NMOS capacitor is placed on each of the two sides of the static latch. In the present invention, the nonvolatile capacitors are NVJRAM cells with many of these NVJRAM cells being placed on one bit line feeding each of the two inputs to the static latch which now becomes a DRAM-like sense latch. Furthermore, the present invention is a high density nonvolatile RAM rather than a static RAM with nonvolatile backup.
Therefore, the present invention is in effect a crosspoint capacitor memory array in which the small programming crosstalk effects inherent in the device of Raffel and Yasaitis have been diminished by the vertical JFET and in which a more sensitive capacitor read mechanism using voltage steps or pulses and the sense latch circuits have been utilized. The read disturb effects inherent in U.S. patent application Ser. No. 228,413 and in Raffel and Yasaitis have been overcome by using a capacitance sense mechanism rather than preparing a nonequilibrium state. The low packing density of the static RAM cell of Saito has been converted into a high packing density DRAM-type cell and the information is always stored in the memory insulator rather than using it only as a nonvolatile backup.
The object of this invention is to provide a nonvolatile random access memory cell for which the operation of reading the nonvolatile state of the cell has an improved (lower) disturbing effect on the nonvolatile state being read, with this improvement being obtained by reducing the reading voltage applied to the cell. Another object is to provide a read mechanism which does not utilize a nonequilibrium read mechanism which is strongly sensitive to dark currents, such as would be the case if a standard DRAM volatile write and read had been used. Another object is to provide a high sensitivity read operation for programmable capacitors which is compatible with the use of sense latches and has a sensitivity which is not affected by the pattern of data programmed at bits along one sense line. Yet another object is to provide a high packing density of programmable capacitors with as few components per cell as possible, having minimum read disturb and pattern sensitivity.